The present invention relates to voltage controlled oscillators (VCOs), especially VCOs and methods of setting VCOs to achieve a desirable locking condition.
Voltage controlled oscillators (VCOs) are typically used in phase locked loops to provide a stable oscillator output which can be varied in frequency across large frequency ranges. For example, VCOs are utilized in receivers to provide a variable oscillator frequency for shifting down the frequency of an input signal having a variable center frequency. VCOs are also utilized in some transmitters to provide a variable oscillator frequency with which to shift up the frequency of a signal to a selected one of plurality of center frequencies.
FIG. 1 is a diagram illustrating a voltage controlled oscillator 10 as arranged in a basic phase locked loop (PLL) 12 according to the prior art. In the PLL shown in FIG. 1, the output frequency fo of the VCO is set by a frequency select input FSEL to a divide by N circuit 14 which functions to divide the output frequency fo down to a reference frequency generated by a reference oscillator 16. The output of the divide by N circuit 14 and the reference oscillator 16 are both input to a phase comparator 18, which outputs a signal representing frequency/phase difference between the two inputs. The difference signal 19 is provided to a loop filter 20, which, in turn, outputs a control voltage 22 that controls the output frequency fo of the VCO 10. In such prior art PLL, the VCO output frequency fo is a multiple N of the output frequency of the reference oscillator. A calibration logic circuit 24 receives the VCO control voltage 22 and further controls operations of the VCO which result in locking the VCO 10.
In addition to controlling the VCO through the control voltage input 22, many VCOs today provide additional granularity of control by separating the frequency range over which the VCO operates into a plurality of frequency bands. Then, the frequency band selection is changed as the VCO moves toward the locked condition. For example, the frequency band of the prior art PLL 12 is changed by a signal 26 output from the calibration logic circuit 24 when the control voltage 22 reaches a maximum value, and the VCO has not yet achieved lock. Such signal 26 is generally referred to as a “coarse calibration” signal. Sometimes, the coarse calibration signal is generated in response to the signal 19 output from the phase comparator 18 to the loop filter 20.
An example of operation of the prior art VCO 10 will now be described. To change the VCO output frequency of the prior art VCO, the frequency select (FSEL) input to the PLL 12 is changed. With reference to FIG. 2, at that time the calibration logic 24 selects the lowest frequency band B1 of the VCO 10 to begin adjusting the VCO settings towards the desired output frequency fo. In FIG. 2, the VCO output frequency fo increases with the vertical scale while the VCO control voltage 22 increases with the horizontal scale. The VCO control voltage is scanned from a lowest (negative voltage) setting 28 through the zero volts setting up to a highest (positive voltage) setting 30 while the calibration logic circuit 24 determines whether lock is achieved. As the highest frequency 32 reached by frequency band B1 is still lower than the desired output frequency fo, a coarse calibration signal 26 is output from the calibration logic circuit 24, which signal increments the frequency band to frequency band B2. The VCO control voltage is then adjusted again beginning from the lowest setting and increasing towards the highest setting to seek an operating point at which the desired output frequency fo is achieved.
This procedure is performed for each successive frequency band and control voltage value until a value of the VCO control voltage is reached at which the desired output frequency fo is achieved. However, as shown in FIG. 2, multiple values 32, 34 and 36 of the VCO control voltage exist at which the desired output frequency fo is achieved, although each setting is associated with a different frequency band setting of the VCO. For example, control voltage setting 32 lies on frequency band 3, while control voltage setting 34 lies on frequency band 4, and control voltage setting 34 lies on frequency band 5. Prior art procedures for determining frequency band and control voltage settings at which to lock the VCO have been problematic. The problems will be described next, with reference to FIGS. 3, 4 and 5.
A first such approach according to the prior art is illustrated in FIG. 3. In such approach, a search for appropriate VCO settings begins from the lowest control voltage setting 40 of the lowest frequency band B1. By operation of the phase locked loop 12, the control voltage is scanned upward within each frequency band, and the frequency band setting is increased one or more times, as needed, until a value 40 of the control voltage is reached which results in the desired output frequency fo. Such control voltage setting and frequency band setting result in the VCO settling at the output frequency fo. However, the calibration logic 24 has not yet determined the final settings to lock the VCO 12.
It is desired that the VCO lock at a control voltage setting that is as close as possible to zero volts. Under such condition, the desired output frequency fo can be most quickly restored after noise and momentary spikes by the automatic action of the PLL. In the approach illustrated in FIG. 3, the VCO 10 selects an appropriate setting by requiring the control voltage 22 to turn negative before the PLL 12 is determined to have finally locked. As a result, the control voltage 40 is rejected as not an appropriate setting. The frequency band is then incremented to band B4, at which time a control voltage value 41 is reached which again results in the desired output frequency fo. However, the control voltage value 41 is rejected as being a positive value, even though the value 41 actually lies close to zero volts. Therefore, the frequency band is incremented again to a higher frequency band B5. Eventually, the control voltage value 42 is reached which results in the desired output frequency fo and is a negative value. However, this time the final control voltage value 42 lies farther from zero volts than the control voltage value 41 that was reached in the lower frequency band B4. This illustrates a problem of the prior art approach in failing to reach a control voltage value near zero volts.
FIG. 4 illustrates VCO locking operation according to another prior art approach. In such approach, the VCO is not required to lock only at a negative control voltage value. Instead, fixed positive and negative threshold levels +Vt and Vt are provided, against which the control voltage value is tested to determine whether an appropriate control voltage setting has been reached. Again, the search for appropriate VCO settings begins from the lowest control voltage setting 48 of the lowest frequency band B1. As shown in FIG. 4, a control voltage value 50 is first reached which results in the desired output frequency fo. This value 50 is then tested against the positive and negative threshold levels +Vt and Vt. Since the value 50 lies outside of the range from to +Vt, it is determined to be an unsuitable setting. The frequency band is therefore incremented to a next higher band B4, and eventually a control voltage value 51 is reached which does fall within the range Vt to +Vt. Under such conditions, the calibration logic 24 of the VCO determines lock to have been achieved, and the control voltage and frequency band settings are therefore maintained from that time on.
FIG. 5 illustrates a problem with the approach described above relative to FIG. 4. As shown in FIG. 5, it happens for some output frequencies fo that there is no control voltage and frequency band setting that falls within the voltage range to +Vt between the fixed threshold levels. As shown in FIG. 5, when the control voltage value 61 is reached which first results in the desired output frequency fo, the calibration logic 24 rejects that control voltage value as unsuitable. The frequency band is then incremented, and an attempt is next made to lock the VCO 12 at the control voltage value 62. However, that value 62 lies below the lower threshold Vt. Therefore, value 62 is also rejected as being an unsuitable control voltage. As a result, the VCO is not permitted to remain at either of the two possible control voltage settings 61 and 62, and fails to lock at any settings.
Accordingly, it would be desirable to provide a VCO which is operable to lock at a control voltage that is desirably close to zero.
It would further be desirable to provide a VCO which is operable to lock at a control voltage falling between a lower threshold and an upper threshold.
It would further be desirable to provide a VCO in which the range between the lower and upper thresholds is widened as needed to allow the VCO to lock at a desirable control voltage value.